1. Field of the Invention
The present invention relates to a semiconductor device and a method for producing the same. In particular, the present invention relates to a semiconductor device having a Panel scale Fan-out package structure in which the thin film wiring step and the assembling step are performed on a large panel scale.
2. Description of the Related Art
Recent years have seen demands for higher functionality and reduced size and weight in electronic equipment, and accordingly, progress has been made in the high-density integration of electronic components and also in high-density mounting, and semiconductor devices used in such electronic equipment have also been becoming increasingly compact in size more than before.
As a method for manufacturing a semiconductor device such as an LSI unit or an IC module, firstly, a plurality of semiconductor chips judged to be good quality by an electrical properties test are arranged and bonded in a prescribed configuration on a supporting plate, with the element circuit surface facing downwards, whereupon, for instance, a resin sheet is arranged thereon and molded by applying heat and pressure, thereby sealing the plurality of semiconductor chips in a lump, whereupon the supporting plate is peeled away, the resin sealed body is cut and machined to a prescribed shape (for example, a circular shape), an insulating material layer is formed on the element circuit surfaces of the semiconductor chips buried in the sealed resin body, openings are formed in accordance with the positions of the electrode pads of semiconductor chips on the insulating material layer, and a wiring layer is then formed on top of the insulating material layer, in addition to which conducting sections (via sections) connected to the electrode pads of the semiconductor chips are formed inside the openings, whereupon a solder resist layer is formed, solder balls, which are to be external electrode terminals, are formed successively, and each semiconductor chip is then cut out individually, one by one, to complete the semiconductor devices (for example, see Japanese Patent Publication No. 2003-197662).
However, in a conventional semiconductor device obtained in this way, when sealing with resin the plurality of semiconductor chips all together, the resin contracts upon curing and since the amount of contraction does not necessarily comply with the design, the positions after curing of the resin may deviate from the design positions, depending on the arrangement positions of the semiconductor chips, and in the semiconductor chips having positional deviation of this kind, positional deviation occurs between the via sections formed in the openings of the insulating material layer and the electrode pads of the semiconductor chips, and hence there is a problem in that connection reliability declines.
A semiconductor device which resolves this problem is described in Japanese Patent Publication No. 2010-219489.
FIG. 8 shows the basic structure of this device.
The semiconductor device 20 comprises a support plate (metal flat plate) 1 constituted by a metal, a semiconductor chip 2 being disposed with an element circuit surface (front surface) facing upwards, on one main surface of the metal flat plate 1, and the surface on the opposite side to the element circuit surface (rear surface) being fixed to the metal flat plate 1 by adhesive 3. Only one insulating material layer 4 is formed on whole of the main surface of the metal flat plate 1 so as to cover the element circuit surface of the semiconductor chip 2. A wiring layer 5 made from a conductive metal, such as copper, is formed on top of this single insulating material layer 4, and one portion thereof is extracted to a peripheral region of the semiconductor chip 2. Furthermore, a conductive portion (via portion) 6 which electrically connects an electrode pad (not illustrated) of the semiconductor chip 2 and the wiring layer 5 is formed on the insulating material layer 4 formed on top of the element circuit surface of the semiconductor chip 2. This conductive portion 6 is formed in an integrated fashion, together with the wiring layer 5. Moreover, a plurality of solder balls 7 which are external electrodes are formed at prescribed positions on the wiring layer 5. Furthermore, a protective layer such as a wiring protection layer (solder resist layer) 8 is formed on top of the insulating material layer 4, and on top of the wiring layer 5 apart from the junctions with the solder balls 7.
This device contributes to the high-density integration and the reduction in weight and size of the electronic components that have been required considerably.